1. Field of the Invention
The present invention relates generally to capacitance modeling methods employed when designing and fabricating microelectronic products. More particularly, the present invention relates to refined capacitance modeling methods employed for designing and fabricating microelectronic products.
2. Description of the Related Art
Common in the microelectronic product fabrication art is the use of modeling methods and apparatus for modeling anticipated microelectronic product electrical performance prior to fabricating microelectronic products. Expected electrical performance modeling is desirable within the context of microelectronic product fabrication since it generally provides for a more efficient and effective process definition when fabricating microelectronic products.
Of particular interest within microelectronic product fabrication are parasitic capacitance modeling methods which are intended to quantify parasitic capacitance between conductor layers which connect and interconnect active devices within microelectronic products. Parasitic capacitance may lead to undesirable increases in microelectronic product operating speed, undesirable decreases in microelectronic product operating speed or undesirable electrical noise within a microelectronic product.
While parasitic capacitance modeling is thus desirable within microelectronic product design and fabrication, it is nonetheless not entirely without problems. In that regard, it is often difficult to accurately model parasitic capacitance within microelectronic products.
It is thus desirable within the microelectronic product fabrication art to provide methods and apparatus which provide for a more accurate parasitic capacitance modeling when designing and fabricating microelectronic products. It is towards the foregoing object that the present invention is directed.
Various parasitic capacitance modeling methods and apparatus have been disclosed within the microelectronic product fabrication art. Included but not limiting among the methods and apparatus are those disclosed within: (1) DeCamp et al., in U.S. Pat. No. 5,761,080 (a parasitic capacitance modeling method and apparatus which provides for partitioning of microelectronic product conductor layers into simpler geometric shapes with respect to which overlap capacitance and fringe capacitance may be determined); and (2) Mehrotra et al., in U.S. Pat. No. 6,061,508 (a parasitic capacitance modeling method and apparatus which provides for three dimensional capacitance determinations as well as two dimensional capacitance determinations).
The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable within the microelectronic product fabrication art are additional methods and apparatus which provide for more accurate parasitic capacitance modeling. It is towards the foregoing object that the present invention is directed.